In semiconductor devices, aluminum and aluminum alloys have been used as the traditional interconnect metallurgies. While aluminum-based metallurgies have been the material of choice for use as metal interconnects over the past years, concern now exists as to whether aluminum will meet the demands required as circuit density and speeds for semiconductor devices increase. Because of these growing concerns, other materials have been investigated as possible replacements for aluminum-based metallurgies.
One highly advantageous material now being considered as a potential replacement for aluminum metallurgies is copper, because of its lower susceptibility to electromigration failure as compared to aluminum, as well as its lower resistivity. Despite these advantages, copper suffers from an important disadvantage. Copper readily diffuses into the surrounding dielectric material during subsequent processing steps. To inhibit the diffusion of copper, copper interconnects are often capped with a diffusion barrier layer. One method of capping involves the use of a conductive barrier layer of tantalum, titanium or tungsten, in pure or alloy form, along the sidewalls and bottom of the copper interconnection. To cap the upper surface of the copper interconnection, a dielectric material such as silicon nitride is typically employed.
A typical interconnect structure using low-k dielectric material and copper interconnects is shown in FIG. 1. The interconnect structure comprises a lower substrate 10 which may contain logic circuit elements such as transistors. A dielectric layer 12, commonly known as an inter-layer dielectric (ILD), overlies the substrate 10. In advanced interconnect structures, ILD layer 12 is preferably a low-k polymeric thermoset material such as SiLK™ (an aromatic hydrocarbon thermosetting polymer available from The Dow Chemical Company). An adhesion promoter layer 11 may be disposed between the substrate 10 and ILD layer 12. A layer of silicon nitride 13 may be disposed on ILD layer 12. Silicon nitride layer 13 is commonly known as a hardmask layer or polish stop layer. At least one conductor 15 is embedded in ILD layer 12. Conductor 15 is typically copper in advanced interconnect structures, but may alternatively be aluminum or other conductive material. A diffusion barrier liner 14 may be disposed between ILD layer 12 and the conductor 15. Diffusion barrier liner 14 is typically comprised of tantalum, titanium, tungsten or nitrides of these metals. The top surface of conductor 15 is made coplanar with the top surface of silicon nitride layer 13, usually by a chemical-mechanical polish (CMP) step. A cap layer 17, also typically of silicon nitride, is disposed on conductor 15 and silicon nitride layer 13. Silicon nitride cap layer 17 acts as a diffusion barrier to prevent diffusion of copper from conductor 15 into the surrounding dielectric material.
A first interconnect level is defined by adhesion promoter layer 11, ILD layer 12, silicon nitride layer 13, diffusion barrier liner 14, conductor 15, and cap layer 17 in the interconnect structure shown in FIG. 1. A second interconnect level, shown above the first interconnect level in FIG. 1, includes adhesion promoter layer 18, ILD layer 19, silicon nitride layer 20, diffusion barrier liner 21, conductor 22, and cap layer 24.
The first and second interconnect levels may be formed by conventional damascene processes. For example, formation of the second interconnect level begins with deposition of adhesion promoter layer 18. Next, the ILD material 19 is deposited onto adhesion promoter layer 18. If the ILD material is a low-k polymeric thermoset material such as SiLK™, the ILD material is typically spin-applied, given a post apply hot bake to remove solvent, and cured at elevated temperature. Next, silicon nitride layer 20 is deposited on the ILD. Silicon nitride layer 20, also known as a hardmask layer or polish stop layer, is patterned by conventional photolithography techniques, and then acts as a mask during subsequent etching of ILD layer 19, adhesion promoter layer 18 and cap layer 17, to form at least one trench and via. The trenches and vias are typically lined with diffusion barrier liner 21. The trenches and vias are then filled with a metal such as copper to form the conductor 22 in a conventional dual damascene process. Excess metal is removed by a CMP process. The silicon nitride layer 20 acts as a polish stop layer during the CMP process. Finally, silicon nitride cap layer 24 is deposited on copper conductor 22 and silicon nitride layer 20.
It is well understood in the semiconductor arts that a pre-clean before cap deposition enhances the reliability of an integration structure by improving the conductor/cap interface. However, the newer low-k and extreme low k (ELK) porous dielectrics are more susceptible to processing damage than conventional ILD layers. One solution is to use a hardmask to cover and protect the ILD. Such a hardmask is typically a permanent part of the interconnect structure, so it affects the effective dielectric constant of the entire ILD stack. Since an ILD hardmask is denser or constructed of higher Z materials than the low-k dielectric, the net effect is to increase the effective dielectric constant of the ILD stack, thereby partially defeating the advantage gained from the low-k dielectric. The hard mask may also require additional processing or tooling.
Therefore, there remains a need for improved methods and systems for protecting low-k dielectrics without increasing the effective dielectric constant of the ILD stack.